(A) Field of the Invention
The present invention relates to technologies for manufacturing multilayer wiring boards used as packages for mounting semiconductor elements (hereinafter referred to as “semiconductor packages”). More specifically, the present invention relates to a semiconductor package containing a capacitor portion using a conductive resin layer formed on a wiring layer, a method of manufacturing the same and a semiconductor device.
(B) Description of the Related Art
In order to meet demands for higher density, semiconductor packages in recent years include wiring patterns which are disposed close to one another. Accordingly, such semiconductor packages would incur problems such as an occurrence of crosstalk noises between a plurality of wiring, or fluctuation of electric potential of power source line and the like. In particular, a package for mounting a semiconductor element for high-frequency use, in which high-speed switching operations are required, tends to incur crosstalk noises along with an increase in frequency or incur switching noises because a switching element therein is turned on and off in a high speed. As a result, electric potential of a power source line and the like tends to vary easily.
Therefore, as a remedy for the foregoing problems, “decoupling” of a signal line or a power source line has been heretofore put into practice. Such decoupling is carried out by adding capacitor elements such as chip capacitors to a package mounting a semiconductor element thereon.
However, in this case, design freedom of wiring patterns may be restricted by provision of the chip capacitors, or an increase in inductance may be incurred due to elongated wiring patterns for connecting the chip capacitors and power/ground terminals of the semiconductor element. As the decoupling effect of the chip capacitor is impaired where the inductance is large, it is preferred to set the inductance as small as possible. In other words, it is desirable to dispose the capacitor elements such as chip capacitors as close to the semiconductor element as possible.
There is also a risk that the package becomes larger and heavier as a whole because the capacitor elements such as chip capacitors are added to the package, which goes against the tide of downsizing and weight saving of semiconductor packages in recent years.
Therefore, instead of adding the capacitor elements such as chip capacitors to the package, it is conceivable to allow the package to contain equivalent capacitor elements (capacitor portions) in order to deal with the above-mentioned inconveniences.
Conventionally, technologies for building the capacitor portion into the package have been limited to a few methods, such as a method of laminating a sheet member containing inorganic filler for improving dielectric constant between wiring layers, as a dielectric layer of the capacitor portion.
As described above, in the conventional semiconductor package, the sheet member made of a high-dielectric material is laminated between the wiring layers as the dielectric layer of the capacitor portions in the case of allowing the package to contain the capacitor elements (the capacitor portions) for exerting the decoupling effect. In this context, it is necessary to form an insulating layer between the wiring layers thicker than the dielectric layer concerned. Accordingly, there arises an inconvenience in that the thickness of the interlayer insulating film cannot be sufficiently made thin.
Such an inconvenience inhibits formation of a low-profile semiconductor package and resultantly goes against the tide of recent demands for providing a high-density equipped semiconductor device while reducing an entire thickness of the package. In addition, costs for an interlayer insulating film rise as a film thickness thereof increases. As a result, there is also a problem of an increase in manufacturing costs of the package.